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MM74HC273 Octal D-Type Flip-Flops with Clear
September 1983 Revised May 2005
MM74HC273 Octal D-Type Flip-Flops with Clear
General Description
The MM74HC273 edge triggered flip-flops utilize advanced silicon-gate CMOS technology to implement D-type flipflops. They possess high noise immunity, low power, and speeds comparable to low power Schottky TTL circuits. This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the LOW-to-HIGH transition of the CLOCK input. The CLEAR input when LOW, sets all outputs to a low state. Each output can drive 10 low power Schottky TTL equivalent loads. The MM74HC273 is functionally as well as pin compatible to the 74LS273. All inputs are protected from damage due to static discharge by diodes to VCC and ground.
Features
s Typical propagation delay: 18 ns s Wide operating voltage range s Low input current: 1 PA maximum s Low quiescent current: 80 PA (74 Series) s Output drive: 10 LS-TTL loads
Ordering Code:
Order Number MM74HC273WM MM74HC273SJ MM74HC273MTC MM74HC273N Package Number M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Top View
(c) 2005 Fairchild Semiconductor Corporation
DS005331
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MM74HC273
Truth Table
(Each Flip-Flop) Inputs Clear L H H H Clock X D X H L X Outputs Q L H L Q0
Logic Diagram
n n
L
H HIGH Level (Steady State) L LOW Level (Steady State) X Don't Care n Transition from LOW-to-HIGH level Q0 The level of Q before the indicated steady state input conditions were established
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MM74HC273
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) VCC VCC VCC 2.0V 4.5V 6.0V 1000 500 400 ns ns ns 0 VCC V 2 Max 6 Units V
0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r25 mA r50 mA 65qC to 150qC
40
85
qC
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC.
DC Electrical Characteristics
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN VIH or VIL Conditions
(Note 4)
VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V TA Typ 1.5 3.15 4.2 0.5 1.35 1.8 2.0 4.5 6.0 4.2 5.7 0 0 0 0.2 0.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 25qC TA
40 to 85qC TA 55 to 125qC
Guaranteed Limits 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4
Units V V V V V V V V V V V V V V V V
|IOUT| d 20 PA
2.0V 4.5V 6.0V
VIN
VIH or VIL 4.5V 6.0V 2.0V 4.5V 6.0V
|IOUT| d 4.0 mA |IOUT| d 5.2 mA VOL Maximum LOW Level Output Voltage VIN VIH or VIL |IOUT| d 20 PA
VIN
VIH or VIL 4.5V 6.0V 6.0V 6.0V
|IOUT| d 4 mA |IOUT| d 5.2 mA IIN ICC Maximum Input Current Maximum Quiescent Supply Current VIN IOUT VCC or GND 0 PA VIN VCC or GND
r0.1
8
r1.0
80
r1.0
160
PA PA
Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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MM74HC273
AC Electrical Characteristics
VCC
5V, TA
25qC, CL
15 pF, tr
tf 6 ns
Conditions Typ 50 18 18 10 10 Guaranteed Limit 30 27 27 20 20 0 16 Units MHz ns ns ns ns ns ns
Symbol fMAX tPHL, tPLH tPHL tREM ts tH tW
Parameter Maximum Operating Frequency Maximum Propagation Delay, Clock to Output Maximum Propagation Delay, Clear to Output Minimum Removal Time, Clear to Clock Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Minimum Pulse Width Clock or Clear
2
10
AC Electrical Characteristics
CL
50 pF, tr
tf 6 ns (unless otherwise specified)
Parameter Conditions VCC 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V 2.0V 4.5V 6.0V (per flip-flop) 28 11 9 45 7 10 10 10 TA Typ 16 74 78 38 14 12 42 19 18 0 0 0 26 7 5 5 27 31 135 27 23 135 27 23 25 5 4 100 20 17 0 0 0 80 16 14 1000 500 400 75 15 13 25qC TA
Symbol fMAX
40 to 85qC TA 55 to 125qC
Guaranteed Limits 4 21 24 170 34 29 170 34 29 32 6 5 125 25 21 0 0 0 100 20 18 1000 500 400 95 19 16 3 18 20 205 41 35 205 41 35 37 7 6 150 30 25 0 0 0 120 24 20 1000 500 400 110 22 19
Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF
Maximum Operating Frequency
tPHL, tPLH
Maximum Propagation Delay, Clock to Output
tPHL
Maximum Propagation Delay, Clear to Output
tREM
Minimum Removal Time Clear to Clock
ts
Minimum Setup Time Data to Clock
tH
Minimum Hold Time Clock to Data
15 6 4
34 11 10
tW
Minimum Pulse Width Clock or Clear
tr, tf
Maximum Input Rise and Fall Time, Clock
tTHL, tTLH
Maximum Output Rise and Fall Time
CPD CIN
Power Dissipation Capacitance (Note 5) Maximum Input Capacitance
Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC.
CPD VCC2f ICC VCC, and the no load dynamic current consumption,
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MM74HC273
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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MM74HC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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MM74HC273
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
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MM74HC273 Octal D-Type Flip-Flops with Clear
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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